1. Field of the Invention
Embodiments of the present invention generally relate to processing substrates. More particularly, embodiments of the invention relate to planarizing a layer by oxidation and removal of the same.
2. Description of the Related Art
In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting, and dielectric materials are deposited on or removed from a surface of a substrate. Thin layers of conducting, semiconducting, and dielectric materials may be deposited by a number of deposition techniques. Common deposition techniques in modern processing include physical vapor deposition (PVD), also known as sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and electro-chemical plating (ECP).
As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization. Planarizing a surface, or “polishing” a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials. Planarization is also useful in forming features on a substrate by removing excess deposited material used to fill the features and to provide an even surface for subsequent levels of metallization and processing. Further, planarization is critical to ensuring proper focusing of photolithography equipment.
Conventional polishing techniques used to planarize wafers include Chemical Mechanical Polishing (CMP), Electro Chemical Mechanical Polishing (ECMP) and the like. Both CMP and ECMP utilize a polishing pad for polishing wafers in a fluid environment. Typically, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with the polishing pad. The carrier assembly provides a controllable pressure to the substrate, thereby pressing the substrate against the polishing pad. The pad is moved relative to the substrate by an external driving force. Polishing is effected by chemical activities, electrical and/or mechanical activities.
However, in some cases conventional polishing techniques have proven inadequate. One example is in the case of a silicon wafer or substrate. Examples of silicon wafers include Epitaxial (epi) wafers and Silicon-On-Insulator (SOI) wafers. Such wafers are normally polished using techniques like CMP, although other methods may also be used. However, while such conventional polishing techniques eliminate nanometer size surface roughness, they can introduce other surface non-uniformities and leave a film with unacceptable variations in thickness.
Therefore, there is a need for a method and apparatus for planarizing materials, particularly silicon.